Designing a Coprocessor for Recurrent Computations

In this paper, we present the design of an application-speci c coprocessor for algorithms that can be modeled as uniform recurrences or \uniformized" a ne recurrences. The coprocessor has a regular array of processors connected to an access-unit for intermediate storage of data. The distinguishing feature of our approach is that we assume the coprocessor to be interfaced to a standard, slow (single-ported) memory with low bandwidth. Hence, good performance is achieved by e ectively exploiting data locality in the applications by the compiler, and the nal architecture is chosen by a tradeo analysis driven by the mapping process. Preliminary results indicate that the coprocessor has signi cantly lower clock rates or higher performance than that of existing RISC processors and is cost-e ective for executing loop computations.